mos管(guan)升压电(dian)路-mos管(guan)升压电(dian)路图及驱动电(dian)路、升压自举(ju)电(dian)路等(deng)详解(jie)-KIA MOS管(guan)
信息来源(yuan)：本(ben)站 日期(qi)：2018-11-08
boost升(sheng)压(ya)(ya)电(dian)路又叫(jiao)step-up converter，是一种(zhong)常见的(de)开关直流升(sheng)压(ya)(ya)电(dian)路，它可以使输(shu)出电(dian)压(ya)(ya)比输(shu)入(ru)电(dian)压(ya)(ya)高。
假定(ding)那(nei)个(ge)开(kai)关（三极管或者mos管）已经断开(kai)了很长时间，所有的元件都处于(yu)理(li)想状态，电容电压(ya)等于(yu)输入电压(ya)。分析升压斩波电路工作原理时，首先假设电路中电感L值很大，电容C值也很大。当(dang)可(ke)控开关(guan)V处于(yu)(yu)(yu)通态(tai)时(shi)，电(dian)(dian)(dian)源E向(xiang)电(dian)(dian)(dian)感(gan)L充电(dian)(dian)(dian)，充电(dian)(dian)(dian)电(dian)(dian)(dian)流基本恒定为(wei)(wei)I1，同时(shi)电(dian)(dian)(dian)容C上(shang)的(de)(de)电(dian)(dian)(dian)压(ya)向(xiang)负(fu)载(zai)供电(dian)(dian)(dian)。因为(wei)(wei)C值很大，基本能(neng)保(bao)持输出电(dian)(dian)(dian)压(ya)uo为(wei)(wei)恒值，记为(wei)(wei)Uo。设(she)V处于(yu)(yu)(yu)通态(tai)的(de)(de)时(shi)间为(wei)(wei)ton，当(dang)V处于(yu)(yu)(yu)断态(tai)时(shi)E和L共同向(xiang)电(dian)(dian)(dian)容C充电(dian)(dian)(dian)并(bing)向(xiang)负(fu)载(zai)提供能(neng)量。设(she)V处于(yu)(yu)(yu)关(guan)断的(de)(de)时(shi)间为(wei)(wei)toff，则在此期(qi)间电(dian)(dian)(dian)感(gan)L释放(fang)的(de)(de)能(neng)量为(wei)(wei)(Uo-E)I1toff。当(dang)电(dian)(dian)(dian)路工作(zuo)于(yu)(yu)(yu)稳态(tai)时(shi)，一个周(zhou)期(qi)T中电(dian)(dian)(dian)感(gan)L积蓄的(de)(de)能(neng)量与释放(fang)的(de)(de)能(neng)量相等。
下面(mian)要分充电和放电两(liang)个部分来说明这个电路：
在(zai)充电(dian)(dian)(dian)(dian)过程中，开关(guan)闭合（三极管导(dao)(dao)通(tong)），等效电(dian)(dian)(dian)(dian)路如图二，开关(guan)（三极管）处用导(dao)(dao)线(xian)代替。这时，输入电(dian)(dian)(dian)(dian)压流过电(dian)(dian)(dian)(dian)感(gan)(gan)。二极管防(fang)止电(dian)(dian)(dian)(dian)容对(dui)地放(fang)电(dian)(dian)(dian)(dian)。由于(yu)输入是直流电(dian)(dian)(dian)(dian)，所以电(dian)(dian)(dian)(dian)感(gan)(gan)上的电(dian)(dian)(dian)(dian)流以一定的比(bi)率(lv)线(xian)性增(zeng)加，这个比(bi)率(lv)跟电(dian)(dian)(dian)(dian)感(gan)(gan)大(da)小有(you)关(guan)。随(sui)着电(dian)(dian)(dian)(dian)感(gan)(gan)电(dian)(dian)(dian)(dian)流增(zeng)加，电(dian)(dian)(dian)(dian)感(gan)(gan)里储存了(le)一些能量。
放电(dian)(dian)(dian)过程如图三(san)，这(zhei)是当开关(guan)断(duan)开（三(san)极管截(jie)止）时(shi)的(de)等效(xiao)电(dian)(dian)(dian)路(lu)。当开关(guan)断(duan)开（三(san)极管截(jie)止）时(shi)，由于(yu)电(dian)(dian)(dian)感(gan)的(de)电(dian)(dian)(dian)流(liu)保持特性，流(liu)经电(dian)(dian)(dian)感(gan)的(de)电(dian)(dian)(dian)流(liu)不会马上变为0，而是缓慢的(de)由充电(dian)(dian)(dian)完毕(bi)时(shi)的(de)值变为0。而原来的(de)电(dian)(dian)(dian)路(lu)已断(duan)开，于(yu)是电(dian)(dian)(dian)感(gan)只能通过新电(dian)(dian)(dian)路(lu)放电(dian)(dian)(dian)，即(ji)电(dian)(dian)(dian)感(gan)开始(shi)给电(dian)(dian)(dian)容充电(dian)(dian)(dian)，电(dian)(dian)(dian)容两端(duan)电(dian)(dian)(dian)压(ya)升高，此时(shi)电(dian)(dian)(dian)压(ya)已经高于(yu)输入(ru)电(dian)(dian)(dian)压(ya)了。升压(ya)完毕(bi)。
说起来升(sheng)压(ya)(ya)过(guo)程(cheng)就(jiu)是一个电感(gan)(gan)的(de)能(neng)(neng)量(liang)传递(di)过(guo)程(cheng)。充(chong)电时，电感(gan)(gan)吸收能(neng)(neng)量(liang)，放(fang)电时电感(gan)(gan)放(fang)出(chu)能(neng)(neng)量(liang)。如果(guo)电容量(liang)足够(gou)大，那(nei)么在(zai)输出(chu)端(duan)就(jiu)可(ke)以(yi)在(zai)放(fang)电过(guo)程(cheng)中(zhong)保持(chi)一个持(chi)续的(de)电流(liu)。如果(guo)这个通断(duan)的(de)过(guo)程(cheng)不断(duan)重复。就(jiu)可(ke)以(yi)在(zai)电容两端(duan)得到高于输入电压(ya)(ya)的(de)电压(ya)(ya)。
MOS管最明(ming)显的(de)(de)特(te)征(zheng)是开(kai)关(guan)特(te)征(zheng)好，因而被普(pu)遍使(shi)用在(zai)需(xu)求电子开(kai)关(guan)的(de)(de)电路中，常见的(de)(de)如(ru)开(kai)关(guan)电源和马达驱(qu)动(dong)，也有(you)照明(ming)调(diao)光(guang)。即兴在(zai)的(de)(de)MOS驱(qu)动(dong)，有(you)几个特(te)殊的(de)(de)要求。
1.低(di)压使用(yong)(yong)：当应用(yong)(yong)5V电源，这时辰如(ru)其应用(yong)(yong)传(chuan)统的(de)图腾柱构造，鉴于三极管(guan)的(de)be有0.7V左(zuo)右的(de)压降，导致现(xian)实终极加以在(zai)gate上的(de)电压除非4.3V。这时辰，咱们选(xuan)用(yong)(yong)标称gate电压4.5V的(de)MOS管(guan)就(jiu)在(zai)必(bi)然的(de)风险。同一的(de)问题(ti)也产(chan)生在(zai)应用(yong)(yong)3V或者其他低(di)压电源的(de)场所(suo)。
2.宽(kuan)电(dian)压使(shi)用：输(shu)入电(dian)压并不(bu)是(shi)一个恒(heng)定值，它会(hui)跟随时(shi)(shi)期(qi)或者(zhe)其(qi)他要素而(er)变(bian)动(dong)(dong)。这个变(bian)动(dong)(dong)导(dao)致(zhi)PWM电(dian)路供(gong)给MOS管(guan)的驱动(dong)(dong)电(dian)压是(shi)不(bu)固定定的。为了(le)让MOS管(guan)在高gate电(dian)压下(xia)(xia)安(an)全，很多MOS管(guan)内(nei)置了(le)固定压管(guan)强行限(xian)度(du)局(ju)限(xian)gate电(dian)压的幅值。在这种(zhong)情(qing)况(kuang)下(xia)(xia)，当供(gong)的驱动(dong)(dong)电(dian)压超(chao)度(du)过固定压管(guan)的电(dian)压，就会(hui)伸起较大的动(dong)(dong)态功耗。同步，如(ru)其(qi)简略的用电(dian)阻(zu)分(fen)压的规律下(xia)(xia)降gate电(dian)压，就会(hui)涌现输(shu)入电(dian)压比较高的时(shi)(shi)辰，MOS管(guan)任务(wu)良(liang)好，而(er)输(shu)入电(dian)压下(xia)(xia)降的时(shi)(shi)辰gate电(dian)压不(bu)可，伸起导(dao)通不(bu)够到底，从而(er)增添(tian)功耗。
3.双电(dian)(dian)(dian)(dian)压(ya)使(shi)用：在(zai)(zai)一些把持(chi)电(dian)(dian)(dian)(dian)路中，逻辑有些应用类型的(de)5V或者3.3V数(shu)字(zi)电(dian)(dian)(dian)(dian)压(ya)，而(er)功比值有些应用12V甚至更高的(de)电(dian)(dian)(dian)(dian)压(ya)。两(liang)个(ge)电(dian)(dian)(dian)(dian)压(ya)选择共位置式连接。这就提出(chu)一个(ge)请(qing)求，需求应用一个(ge)电(dian)(dian)(dian)(dian)路，让低压(ya)侧(ce)能行(xing)有效(xiao)的(de)把持(chi)压(ya)服侧(ce)的(de)MOS管(guan)，同(tong)步压(ya)服侧(ce)的(de)MOS管(guan)也同(tong)在(zai)(zai)这三种(zhong)情况(kuang)下，图腾柱构造(zao)无(wu)法满意出(chu)口请(qing)求，而(er)很多(duo)即(ji)兴成的(de)MOS驱动(dong)IC，如同(tong)也没有包含gate电(dian)(dian)(dian)(dian)压(ya)限度局限的(de)构造(zao)。
电路图如次：
用于NMOS的(de)驱动电(dian)路
用于PMOS的驱动电路(lu)
只针对(dui)(dui)NMOS驱(qu)动电(dian)(dian)路做一(yi)个(ge)简略辨析：Vl和(he)Vh区别(bie)是(shi)低(di)(di)端(duan)(duan)和(he)高(gao)端(duan)(duan)的(de)电(dian)(dian)源(yuan)，两(liang)个(ge)电(dian)(dian)压(ya)可以(yi)是(shi)相通(tong)的(de)，只是(shi)Vl不(bu)应当超度过(guo)Vh。Q1和(he)Q2结合了一(yi)个(ge)反置的(de)图腾柱，用来(lai)实即兴(xing)割(ge)裂，同(tong)步(bu)确保两(liang)只驱(qu)动管Q3和(he)Q4不(bu)会同(tong)步(bu)导(dao)通(tong)。R2和(he)R3供了PWM电(dian)(dian)压(ya)基(ji)(ji)准(zhun)，经过(guo)转变这个(ge)基(ji)(ji)准(zhun)，可以(yi)让(rang)电(dian)(dian)路任务在PWM记号波形比(bi)较(jiao)峭拔的(de)位置。Q3和(he)Q4用来(lai)供驱(qu)动电(dian)(dian)流动，鉴于导(dao)通(tong)的(de)时辰，Q3和(he)Q4对(dui)(dui)立(li)Vh和(he)GND最低(di)(di)都除非一(yi)个(ge)Vce的(de)压(ya)降(jiang)，这个(ge)压(ya)降(jiang)通(tong)常除非0.3V左右(you)，大(da)大(da)低(di)(di)于0.7V的(de)Vce。R5和(he)R6是(shi)反馈(kui)电(dian)(dian)阻，用于对(dui)(dui)gate电(dian)(dian)压(ya)举行采样(yang)，采样(yang)后的(de)电(dian)(dian)压(ya)经过(guo)Q5对(dui)(dui)Q1和(he)Q2的(de)基(ji)(ji)极发(fa)出一(yi)个(ge)激(ji)烈的(de)负反馈(kui)，从而把gate电(dian)(dian)压(ya)限(xian)度局限(xian)在一(yi)个(ge)有限(xian)的(de)数(shu)值。这个(ge)数(shu)值可以(yi)经过(guo)R5和(he)R6来(lai)调整。
mos管升压电路的(de)规(gui)律图(tu)如图(tu)1所示。所谓(wei)的(de)自(zi)举升压规(gui)律执意，在输入(ru)(ru)端IN输入(ru)(ru)一个方波记号(hao)，使用电容Cboot将A点(dian)电压抬升至(zhi)高于(yu)VDD的(de)电平，这么(me)就可以在B端出口(kou)一个与(yu)信号(hao)输入(ru)(ru)反(fan)相，且(qie)高电平高于(yu)VDD的(de)方波记号(hao)。具体(ti)任(ren)务规(gui)律如次：
当VIN为(wei)高电(dian)平(ping)(ping)时，NMOS管N1导通(tong)，PMOS管P1截止，C点电(dian)位为(wei)低电(dian)平(ping)(ping)。同(tong)步N2导通(tong)，P2的(de)(de)栅极(ji)电(dian)位为(wei)低电(dian)平(ping)(ping)，则P2导通(tong)。这(zhei)就使得此(ci)刻(ke)A点电(dian)位约为(wei)VDD，电(dian)容Cboot两端电(dian)压(ya)UC≈VDD。鉴于N3导通(tong)，P4截止，因而(er)B点的(de)(de)电(dian)位为(wei)低电(dian)平(ping)(ping)。这(zhei)段时期称为(wei)预充电(dian)周期。
当VIN变(bian)为(wei)低电(dian)(dian)(dian)平(ping)时(shi)，NMOS管(guan)N1截止，PMOS管(guan)P1导(dao)通(tong)，C点(dian)电(dian)(dian)(dian)位(wei)为(wei)高电(dian)(dian)(dian)平(ping)，约为(wei)VDD。同(tong)步N2、N3截止，P3导(dao)通(tong)。这使得P2的栅极电(dian)(dian)(dian)位(wei)升天，P2截止。此刻(ke)A点(dian)电(dian)(dian)(dian)位(wei)等(deng)同(tong)C点(dian)电(dian)(dian)(dian)位(wei)加以(yi)上电(dian)(dian)(dian)容Cboot两端(duan)电(dian)(dian)(dian)压，约为(wei)2VDD。同(tong)时(shi)P4导(dao)通(tong)，故(gu)此B点(dian)出(chu)口高电(dian)(dian)(dian)平(ping)，且高于VDD。这段(duan)时(shi)期(qi)称为(wei)自举升压周期(qi)。
现实上，B点电(dian)位与负(fu)载电(dian)容和电(dian)容Cboot的大(da)小关于，可以依据设计(ji)需求(qiu)调(diao)理。具(ju)体相(xiang)干将在绍介电(dian)路具(ju)体设计(ji)时仔细议论。在图(tu)(tu)2中给(ji)出了输入端IN电(dian)位与A、B两(liang)点电(dian)位相(xiang)干的表图(tu)(tu)。
图3中(zhong)给出(chu)(chu)了(le)驱(qu)动电(dian)路(lu)的电(dian)路(lu)图。驱(qu)动电(dian)路(lu)选择(ze)Totem出(chu)(chu)口构造设(she)计(ji)，上拉驱(qu)动管(guan)为(wei)(wei)NMOS管(guan)N4、晶体管(guan)Q1和PMOS管(guan)P5。下拉驱(qu)动管(guan)为(wei)(wei)NMOS管(guan)N5。图中(zhong)CL为(wei)(wei)负载电(dian)容，Cpar为(wei)(wei)B点的寄生(sheng)电(dian)容。虚(xu)线框(kuang)内的电(dian)路(lu)为(wei)(wei)自(zi)举升(sheng)压(ya)电(dian)路(lu)。
本驱(qu)动电路的(de)设计(ji)思惟是，使(shi)用自举(ju)升压构造将上拉驱(qu)动管(guan)(guan)N4的(de)栅极(B点)电位(wei)抬(tai)升，使(shi)得UB>VDD+VTH，则NMOS管(guan)(guan)N4任务在线性(xing)区，使(shi)得VDSN4大大减少(shao)，终(zhong)极可以实即兴驱(qu)动出口高电平(ping)达成VDD。而在出口低(di)电平(ping)时，下拉驱(qu)动管(guan)(guan)自己就任务在线性(xing)区，可以确保出口低(di)电平(ping)位(wei)GND。故(gu)此无(wu)需增添自举(ju)电路也能(neng)达成设计(ji)请(qing)求。
思索(suo)到(dao)此驱(qu)动(dong)(dong)电(dian)(dian)(dian)路使用于升压(ya)型DC-DC替(ti)换器(qi)的开关管(guan)驱(qu)动(dong)(dong)，负(fu)载电(dian)(dian)(dian)容CL很大，一般能(neng)达成几十皮法，还需求进一步增(zeng)(zeng)添(tian)出口电(dian)(dian)(dian)流动(dong)(dong)能(neng)力，故此增(zeng)(zeng)添(tian)了(le)晶体管(guan)Q1作为上拉驱(qu)动(dong)(dong)管(guan)。这(zhei)么在输入端由高电(dian)(dian)(dian)平变(bian)为低电(dian)(dian)(dian)平时(shi)，Q1导通，由N4、Q1同步供(gong)电(dian)(dian)(dian)流动(dong)(dong)，OUT端电(dian)(dian)(dian)位(wei)神速(su)上升，当OUT端电(dian)(dian)(dian)位(wei)上升到(dao)VDD-VBE时(shi)，Q1截止，N4持续供(gong)电(dian)(dian)(dian)流动(dong)(dong)对负(fu)载电(dian)(dian)(dian)容充电(dian)(dian)(dian)，直(zhi)到(dao)OUT端电(dian)(dian)(dian)压(ya)达成VDD。
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